//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : over sample the input data with 8-phases 311M clock
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths

module   SOH4_TOP(
   input                         SOH4_RESET,
   input                         SOH4_RCLK,
   input                         SOH4_TCLK,

   input                         MPI_CLK,
   input[8:0]                    MPI_ADDR,
   input                         MPI_CS,
   input                         MPI_WE,
   input[15:0]                   MPI_WD,
   output[15:0]                  MPI_RD,

   input[7:0]                    FRM4_IN_RDATA,
   input                         FRM4_IN_RDEN,
   input[1:0]                    FRM4_IN_RFMCNT4,
   input[8:0]                    FRM4_IN_RFMCNT270,
   input[3:0]                    FRM4_IN_RFMCNT9,

   output[7:0]                   SOH4_OUT_RDATA,
   output                        SOH4_OUT_RDEN,
   output[1:0]                   SOH4_OUT_RFMCNT4,
   output[8:0]                   SOH4_OUT_RFMCNT270,
   output[3:0]                   SOH4_OUT_RFMCNT9,

   input[7:0]                    SOH4_IN_TDATA,
   input[1:0]                    SOH4_IN_TFMCNT4,
   input[8:0]                    SOH4_IN_TFMCNT270,
   input[3:0]                    SOH4_IN_TFMCNT9,

   output[7:0]                   FRM4_OUT_TDATA,
   output[1:0]                   FRM4_OUT_TFMCNT4,
   output[8:0]                   FRM4_OUT_TFMCNT270,
   output[3:0]                   FRM4_OUT_TFMCNT9
   );


wire[4:0]                        MPI_OBSID_ADDR;
wire                             MPI_OBSID_WE;
wire[7:0]                        MPI_OBSID_WD;
wire[7:0]                        MPI_OBSID_RD;

wire                             MPI_OBSIA_WE;
wire[8:0]                        MPI_OBSIA_WD;
wire[6:0]                        MPI_OBSIA_ADDR;
wire[8:0]                        MPI_OBSIA_RD;

wire[1:0]                        OBSIA_FMCNT4;
wire[8:0]                        OBSIA_FMCNT270;
wire[3:0]                        OBSIA_FMCNT9;
wire[7:0]                        OBSIA_DATA;

wire[1:0]                        TB2_FMCNT4;
wire[8:0]                        TB2_FMCNT270;
wire[3:0]                        TB2_FMCNT9;
wire[7:0]                        TB2_DATA;



   assign SOH4_OUT_RDATA[7:0]    = FRM4_IN_RDATA[7:0];
   assign SOH4_OUT_RDEN          = FRM4_IN_RDEN;
   assign SOH4_OUT_RFMCNT4[1:0]  = FRM4_IN_RFMCNT4[1:0];
   assign SOH4_OUT_RFMCNT270[8:0]= FRM4_IN_RFMCNT270[8:0];
   assign SOH4_OUT_RFMCNT9[3:0]  = FRM4_IN_RFMCNT9[3:0];



wire          OBSID_OUT_FP;
wire          OBSID_OUT_DEN;
wire[7:0]     OBSID_OUT_DATA;

wire[2:0]     DSIF_OUT_SECTOR_ADDR;
wire[4:0]     DSIF_OUT_BYTE_ADDR;
wire[7:0]     DSIF_IN_DATA_0, DSIF_IN_DATA_1, DSIF_IN_DATA_2, DSIF_IN_DATA_3;

wire          OBSI_IN_FP;
wire          OBSI_IN_DEN;
wire[7:0]     OBSI_IN_DATA;

SOH4_MPI                         INST_SOH4_MPI(
   .SOH4_RESET                   ( SOH4_RESET ),

   .MPI_CLK                      ( MPI_CLK ),
   .MPI_ADDR                     ( MPI_ADDR[8:0] ),
   .MPI_CS                       ( MPI_CS ),
   .MPI_WE                       ( MPI_WE ),
   .MPI_WD                       ( MPI_WD[15:0] ),
   .MPI_RD                       ( MPI_RD[15:0] ),

   .MPI_OBSID_ADDR               ( MPI_OBSID_ADDR[4:0] ),
   .MPI_OBSID_WE                 ( MPI_OBSID_WE ),
   .MPI_OBSID_WD                 ( MPI_OBSID_WD[7:0] ),
   .MPI_OBSID_RD                 ( MPI_OBSID_RD[7:0] ),

   .MPI_OBSIA_WE                 ( MPI_OBSIA_WE ),
   .MPI_OBSIA_WD                 ( MPI_OBSIA_WD[8:0] ),
   .MPI_OBSIA_ADDR               ( MPI_OBSIA_ADDR[6:0] ),
   .MPI_OBSIA_RD                 ( MPI_OBSIA_RD[8:0] ),

   .DEBUG_0                      ( DEBUG_0 )
   );

SOH4_OBSID                       INST_SOH4_OBSID(
   .SOH4_RESET                   ( SOH4_RESET ),
   .SOH4_RCLK                    ( SOH4_RCLK ),

   .OBSID_IN_RDATA               ( FRM4_IN_RDATA[7:0] ),
   .OBSID_IN_RDEN                ( FRM4_IN_RDEN ),
   .OBSID_IN_RFMCNT4             ( FRM4_IN_RFMCNT4[1:0] ),
   .OBSID_IN_RFMCNT270           ( FRM4_IN_RFMCNT270[8:0] ),
   .OBSID_IN_RFMCNT9             ( FRM4_IN_RFMCNT9[3:0] ),

   .OBSID_OUT_FP                 ( OBSID_OUT_FP ),
   .OBSID_OUT_DEN                ( OBSID_OUT_DEN ),
   .OBSID_OUT_DATA               ( OBSID_OUT_DATA[7:0] ),

   .MPI_CLK                      ( MPI_CLK ),
   .MPI_OBSID_ADDR               ( MPI_OBSID_ADDR[4:0] ),
   .MPI_OBSID_WE                 ( MPI_OBSID_WE ),
   .MPI_OBSID_WD                 ( MPI_OBSID_WD[7:0] ),
   .MPI_OBSID_RD                 ( MPI_OBSID_RD[7:0] )
   );

OBSI_DROP                        INST_OBSI_DROP(
   .OBSI_RESET                   ( SOH4_RESET ),

   .OBDR_CLK                   ( SOH4_RCLK ),
   .OBDR_IN_FP                   ( OBSID_OUT_FP ),
   .OBDR_IN_DATA                   ( OBSID_OUT_DATA[7:0] ),
   .OBDR_IN_DEN                   ( OBSID_OUT_DEN ),

   .OBSI_SYSCLK77                   ( SOH4_TCLK ),
   .DSIF_IN_SECTOR_ADDR                   ( DSIF_OUT_SECTOR_ADDR[2:0] ),
   .DSIF_IN_BYTE_ADDR                   ( DSIF_OUT_BYTE_ADDR[4:0] ),
   .DSIF_OUT_DATA                   ( DSIF_IN_DATA_0[7:0] )
   );

OBIS_DSIF                        INST_OBIS_DSIF(
   .OBSI_RESET                   ( SOH4_RESET ),

   .OBSI_SYSCLK77                   ( SOH4_TCLK ),
   .OBSI_SYSFP                   (  ),
 

   .DSIF_OUT_SECTOR_ADDR                   ( DSIF_OUT_SECTOR_ADDR[2:0] ),
   .DSIF_OUT_BYTE_ADDR                   ( DSIF_OUT_BYTE_ADDR[4:0] ),
   .DSIF_IN_DATA_0                   ( DSIF_IN_DATA_0[7:0] ),
   .DSIF_IN_DATA_1                   ( DSIF_IN_DATA_1[7:0] ),
   .DSIF_IN_DATA_2                   ( DSIF_IN_DATA_2[7:0] ),
   .DSIF_IN_DATA_3                   ( DSIF_IN_DATA_3[7:0] ),

   .MPI_CLK                   (  ),
   .MPI_CF_ADDR                   (  ),
   .MPI_CF_WE                   (  ),
   .MPI_CF_WD                   (  ),
   .MPI_CF_RD                   (  ),

   .OBSI_TXD                   ( OBSI_TXD )
    );


OBSI_ASIF                        INST_OBSI_ASIF(
   .OBSI_RESET                   ( DEBUG_0 ),
   .OBSI_SYSCLK77                ( SOH4_TCLK ),

   .OBSI_RXD                     ( OBSI_TXD ),

   .S2P_OUT_BYTE_DATA            (  ),
   .S2P_OUT_BYTE_EN              (  ),
   .S2P_OUT_BYTE_CNT             (  ),

   .ASIF_OUT_FP_0                ( OBSI_IN_FP ),
   .ASIF_OUT_FP_1                (  ),
   .ASIF_OUT_FP_2                (  ),
   .ASIF_OUT_FP_3                (  ),
   .ASIF_OUT_DEN_0               ( OBSI_IN_DEN ),
   .ASIF_OUT_DEN_1               (  ),
   .ASIF_OUT_DEN_2               (  ),
   .ASIF_OUT_DEN_3               (  ),
   .ASIF_OUT_DATA_0              ( OBSI_IN_DATA[7:0] ),
   .ASIF_OUT_DATA_1              (  ),
   .ASIF_OUT_DATA_2              (  ),
   .ASIF_OUT_DATA_3              (  )
    );



// Tx overhead byte control
SOH4_OBSIA                       INST_SOH4_OBSIA(
   .SOH4_RESET                   ( SOH4_RESET ),
   .SOH4_TCLK                    ( SOH4_TCLK ),

   .OBSI_CLK                     ( SOH4_TCLK ),
   .OBSI_IN_FP                   ( OBSI_IN_FP ),
   .OBSI_IN_DEN                  ( OBSI_IN_DEN ),
   .OBSI_IN_DATA                 ( OBSI_IN_DATA[7:0] ),

   .MPI_CLK                      ( MPI_CLK ),
   .MPI_OBSIA_WE                 ( MPI_OBSIA_WE ),
   .MPI_OBSIA_WD                 ( MPI_OBSIA_WD[8:0] ),
   .MPI_OBSIA_ADDR               ( MPI_OBSIA_ADDR[6:0] ),
   .MPI_OBSIA_RD                 ( MPI_OBSIA_RD[8:0] ),

   .OBSIA_IN_FMCNT4              ( SOH4_IN_TFMCNT4[1:0] ),
   .OBSIA_IN_FMCNT270            ( SOH4_IN_TFMCNT270[8:0] ),
   .OBSIA_IN_FMCNT9              ( SOH4_IN_TFMCNT9[3:0] ),
   .OBSIA_IN_DATA                ( SOH4_IN_TDATA[7:0] ),

   .OBSIA_OUT_FMCNT4             ( OBSIA_FMCNT4[1:0] ),
   .OBSIA_OUT_FMCNT270           ( OBSIA_FMCNT270[8:0] ),
   .OBSIA_OUT_FMCNT9             ( OBSIA_FMCNT9[3:0] ),
   .OBSIA_OUT_DATA               ( OBSIA_DATA[7:0] )
   );

SOH4_TB2                         INST_SOH4_TB2(
   .SOH4_RESET                   ( SOH4_RESET ),
   .SOH4_TCLK                    ( SOH4_TCLK ),

   .TB2_IN_FMCNT4                ( OBSIA_FMCNT4[1:0] ),
   .TB2_IN_FMCNT270              ( OBSIA_FMCNT270[8:0] ),
   .TB2_IN_FMCNT9                ( OBSIA_FMCNT9[3:0] ),
   .TB2_IN_DATA                  ( OBSIA_DATA[7:0] ),

   .TB2_OUT_FMCNT4               ( TB2_FMCNT4[1:0] ),
   .TB2_OUT_FMCNT270             ( TB2_FMCNT270[8:0] ),
   .TB2_OUT_FMCNT9               ( TB2_FMCNT9[3:0] ),
   .TB2_OUT_DATA                 ( TB2_DATA[7:0] )
   );

  assign FRM4_OUT_TFMCNT4[1:0]   = TB2_FMCNT4[1:0];
  assign FRM4_OUT_TFMCNT270[8:0] = TB2_FMCNT270[8:0];
  assign FRM4_OUT_TFMCNT9[3:0]   = TB2_FMCNT9[3:0];
  assign FRM4_OUT_TDATA[7:0]     = TB2_DATA[7:0];

endmodule
